Publications
Selected research papers and publication highlights.
Research Papers
Here are papers listed on my Google Scholar profile.
Someone† denotes equal contributions; Someone denotes corresponding authors.
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[MICRO’26] Zengshi Wang, Zhuoyuan Yang, Wenbin Liao, Xin Yang, Xiaoyan Xiang, Jianyi Meng, Chao Fu, Jun Han. “SPMC: Speculative Multicast for GPU Address Translation Sharing”
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[TC’26] Zhiyuan Zhang, Jialin Liu, Zengshi Wang, Kanheng Jiang, Chao Fu, Jun Han. “Constructing Virtual FIFOs in CPU Cache Hierarchy for Software Data Plane Orchestration”
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[ISCA’26] Chao Fu†, Jingyang Zheng†, Xinliu He, Xiangqi Dong, Zheng Cao, Yuning Zhan, Wenzhong Bao, Peng Zhou, Jun Han. TDMSim: Enabling High-Density and Energy-Efficient GPU DRAM Caches with 2D-Materials for Data-Intensive Applications
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[TACO’25] Kanheng Jiang, Yongxin Lyu, Zhiyuan Zhang, Zengshi Wang, Chao Fu, Jun Han. “Thoth: Uncovering Data-Dependent Memory Access Patterns via Annotation-Directed Load Sampling”
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[MEJ’26] Kaixuan Wang, Jiang Wang, Chao Fu, Jun Han. “SAVP: Self-validating secure speculation via address-based value prediction”
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[DATE’26] Zengshi Wang, Zhiyuan Zhang, Zhuoyuan Yang, Kanheng Jiang, Chao Fu, Jun Han. “Khepri: Crystallizing TAGE for Memory Efficient Prewarm in Serverless Computing”
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[TCAD’26] Chao Fu, Li Wan, Yufan Jia, Zhiyuan Zhang, Kanheng Jiang, Jun Han. “Homonoia: Reinventing underutilized cross-level cache resource using reinforcement learning”
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[TCAD’25] Yufan Jia, Zhiyuan Zhang, Chao Fu, Li Wan, Jun Han. “PCMT: Prioritizing Coherence Message Types for NoC Protocol-level Deadlock Freedom”
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[ASICON’25] Jialin Liu, Zhiyuan Zhang, Chao Fu, Jun Han. “BIND: A Batch Cache-Invalidation Framework Based on Doorbell Mechanism”
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[FPL’24] Chao Fu, Zengshi Wang, Jun Han. “Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification”
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[TPDS’22] Chao Fu, Li Wan, Jun Han. “Losatm: A hardware transactional memory integrated with a low-overhead scenario-awareness conflict manager”
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[MEJ’21] Chao Fu, Yuchao Zhou, Jun Han. “A hardware-efficient dual-source data replication and local broadcast mechanism in distributed shared caches”
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[JSA’25] Li Wan, Zhiyuan Zhang, Chao Fu, Qiang Li, Jun Han. “BoostTM: Best-effort performance guarantees in best-effort hardware transactional memory for distributed manycore architectures”
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[IPDPS’24] Li Wan, Chao Fu, Qiang Li, Jun Han. “LockillerTM: Enhancing performance lower bounds in best-effort hardware transactional memory”
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[ASICON’23] Zengshi Wang, Chao Fu, Jun Han. “Coupled data prefetch and cache partitioning scheme for CPU-accelerator system”
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[MCSoC’21] Zikang Zhou, Chao Fu, Ruiqi Xie, Jun Han. “A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations”