Invited Talks

Presents the Physical AI Data Intelligence Engine at the Shanghai Regional of the 2026 Shaoxing Education–Technology–Talent Innovation Commercialization Competition

Shanghai, China

The presentation introduces a full-stack data infrastructure that transforms real-world scenes and human actions into high-quality training data for Physical AI.

Gave an oral presentation at the 53rd IEEE/ACM International Symposium on Computer Architecture (ISCA 2026)

Raleigh, America

Presented our work on TDMSim in a 20-minute conference talk, highlighting how 2D-material DRAM caches can bridge device-level innovation and system-level GPU architecture optimization for data-intensive workloads.

Invited Lecturer for RISC-V SoC Design and Chip Architecture Training

Shenzhen, China

Gave a three-day invited training course that bridged RISC-V architecture fundamentals with practical processor and SoC design experiments, helping participants build an end-to-end understanding from theory to implementation.

Invited Talk on Heterogeneous Parallel Computing Systems for Low-Altitude UAVs

Zhuhai, China

Delivered an invited talk at the 2025 RISC-V Industry Development Conference, introducing a RISC-V-based heterogeneous parallel computing system for low-altitude UAVs that integrates multi-level parallel architecture, domain-specific accelerator IPs, and hardware/software-in-the-loop simulation.

Invited Talk on Hardware-in-the-Loop Co-Simulation for Embodied Intelligence

Taiyuan, China

Gave a conference talk at the 29th CCF Annual Conference on Computer Engineering and Technology, introducing a unified simulation flow that integrates AirSim, gem5, and FPGA-based hardware validation to bridge physical-world interaction, AI algorithm execution, and processor architecture exploration for embodied intelligent systems.

Oral Presentation on gem5–FPGA Co-Simulation for Efficient SoC Verification and Architecture Exploration

Turin, Italy

Presented our work on Chimera at FPL 2024, introducing a software–hardware co-simulation framework that combines the flexibility of gem5 with FPGA-based RTL execution to accelerate IP verification and architecture exploration in realistic SoC environments.

Invited Poster on Scenario-Aware Hardware Transactional Memory

Shanghai, China

Presented an invited poster at the Huawei Wireless Professor Forum on LosaTM, a low-overhead scenario-aware conflict manager for hardware transactional memory that improves multicore concurrency by adaptively handling false conflicts, capacity overflows, unfairness competition, and friendly-fire conflict scenarios.